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PART NUMBER:
± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
KXTF9-4100
Rev. 6
Jun-2011
TILT_TIMER
This register is the initial count register for the tilt position state timer (0 to 255 counts). Every count is
calculated as 1/ODR delay period, where the ODR is user-defined per Table 14. A new state must be
valid as many measurement periods before the change is accepted. Note that to properly change the
value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
TSC7
Bit7
R/W
TSC6
Bit6
R/W
TSC5
Bit5
R/W
TSC4
Bit4
R/W
TSC3
Bit3
R/W
TSC2
Bit2
R/W
TSC1
Bit1
R/W
TSC0
Bit0
Reset Value
00000000
I C Address: 0x28h
2
WUF_TIMER
This register is the initial count register for the motion detection timer (0 to 255 counts). Every count is
calculated as 1/ODR delay period, where the ODR is user-defined per Table 16. A new state must be
valid as many measurement periods before the change is accepted. Note that to properly change the
value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
WUFC7
Bit7
R/W
WUFC6
Bit6
R/W
WUFC5
Bit5
R/W
WUFC4
Bit4
R/W
WUFC3
Bit3
R/W
WUFC2
Bit2
R/W
WUFC1
Bit1
R/W
WUFC0
Bit0
Reset Value
00000000
I C Address: 0x29h
2
TDT_TIMER
This register contains counter information for the detection of a double tap event. Every count is
calculated as 1/ODR delay period, where the ODR is user-defined per Table 15. TDT_TIMER
represents the minimum time separation between the first tap and the second tap in a double tap
event. The Kionix recommended default value is 0.3 seconds (0x78h). Note that to properly change
the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”.
R/W
TDTC7
Bit7
R/W
TDTC6
Bit6
R/W
TDTC5
Bit5
R/W
TDTC4
Bit4
R/W
TDTC3
Bit3
R/W
TDTC2
Bit2
R/W
TDTC1
Bit1
R/W
TDTC0
Bit0
Reset Value
01111000
I C Address: 0x2Bh
2
36 Thornwood Dr. – Ithaca, NY 14850
tel: 607-257-1080 – fax:607-257-1146
www.kionix.com - info@kionix.com
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